In the semiconductor industry, electronic devices including semiconductor chips and wafers or semiconductor chip carriers, vertical interconnection to the next packaging level, whether chip carriers or stacked chips, may be packaged by the use of through-silicon vias (labeled TSVs). Various techniques are known to create TSVs, as well as to stack chips to form a multi-story chip structure that is sometimes referred to as a 3-D chip stack, allowing reduced die-to-die signal transmission distance and enabling a large increase in the number of links that may be established between dies.
Small-sized packages, as provided by 3-D chip stacks using TSVs, are in high demand for a variety of applications, such as cell phones, digital cameras, PDAs, GPSs, laptop computers, and the like. The continuing growth of these applications requires on-going efforts to boost performance, broaden functionalities, reduce cost and increase packaging densities.
One of many difficulties with such structures is how to synchronize the clock signal among the various chips forming the stack once they are assembled. The aforementioned difficulty may not necessarily extend to all the chip packages if the chips do not operate in a synchronous manner. By way of example, if the chips in the 3-D-stack are used for mass storage, it is not necessary that they be synchronized with each other. However, if each chip perform the function of a processor such as a high-speed multi-processor system or when each chip is a component of a processor, then the synchronization between the chips becomes critical.
The prior art represented by, e.g., U.S. Pat. No. 5,760,478 to Bozso, et al., or U.S. Pat. No. 6,040,203, likewise issued to Bozso et al., respectively describe a precise and highly controllable clock-distribution network constructed on one active substrate to distribute clock signals with minimal skew to another active substrate by connecting the substrates together face-to-face using flip-chip technology. This approach is only valid for two chips bonded face-to-face to each other, and is further limited by not being able to handle the clock skew when a plurality of chips are assembled in 3-D stack where clock signals must travel through many levels of chips and TSVs before it arrives at each chip.